Area Efficient Parallel Multipliers Using Pass Transistor Logic (PTL)

In recent years, total power dissipation and area are one of the most important challenges in VLSI design. By reducing the number of transistors in the circuits and the design structures are may occupied small area and ultra-low power design. In this project based on AND gates and full adders are designed using pass transistor logic (PTL) and different techniques are used for low power in AND Gate, full adder and multipliers. The main aim of this paper is to reduce the power dissipation and area by reducing the transistors. In this project various types of parallel multiplier designs are performed. Multipliers are the major sources of power dissipation in DSP applications. The design analysis of delay and power comparison of the low power using different types of AND gates and multipliers. The designs are implemented delay and power results are obtained using Mentor Graphics EDA tool. The model technology file 0.18 um is use this design. The results show that the transistor counts, delay and the power required are significantly concentrated in the design.